The Netter object provides services related to network extraction from a layout. The relevant methods of this object are available as global functions too where they act on a default incarnation of the netter. Usually it's not required to instantiate a Netter object, but it serves as a container for this functionality.
# create a new Netter object: nx = netter nx.connect(poly, contact) ...
Network formation:
A basic service the Netter object provides is the formation of connected networks of conductive shapes (netting). To do so, the Netter must be given a connection specification. This happens by calling "connect" with two polygon layers. The Netter will then regard all overlaps of shapes on these layers as connections between the respective materials. Networks are the basis for netlist extraction, network geometry deduction and the antenna check.
Connections can be cleared with "clear_connections". If not, connections add atop of the already defined ones. Here is an example for the antenna check:
# build connction of poly+gate to metal1 connect(gate, poly) connect(poly, contact) connect(contact, metal1) # runs an antenna check for metal1 with a ratio of 50 m1_antenna_errors = antenna_check(gate, metal1, 50.0) # add connections to metal2 connect(metal1, via1) connect(via1, metal2) # runs an antenna check for metal2 with a ratio of 70.0 m2_antenna_errors = antenna_check(gate, metal2, 70.0) # this will remove all connections made clear_connections ...
Further functionality of the Netter object:
More methods will be added in the future to support network-related features.
Usage:
The antenna check is used to avoid plasma induced damage. Physically, the damage happes if during the manufacturing of a metal layer with plasma etching charge accumulates on the metal islands. On reaching a certain threshold, this charge may discarge over gate oxide attached of devices attached to such metal areas hence damaging it.
Antenna checks are performed by collecting all connected nets up to a certain metal layer and then computing the area of all metal shapes and all connected gates of a certain kind (e.g. thin and thick oxide gates). The ratio of metal area divided by the gate area must not exceed a certain threshold.
A simple antenna check is this:
poly = ... # poly layer diff = ... # diffusion layer contact = ... # contact layer metal1 = ... # metal layer # compute gate area gate = poly & diff # note that gate and poly have to be included - gate is # a subset of poly, but forms the sensitive area connect(gate, poly) connect(poly, contact) connect(contact, metal1) errors = antenna_check(gate, metal1, 50.0)
Usually antenna checks apply to multiple metal layers. In this case, the connectivity needs to be extended after the first check to include the next metal layers. This can be achieved with incremental connects:
# provide connections up to metal1 connect(gate, poly) connect(poly, contact) connect(contact, metal1) metal1_errors = antenna_check(gate, metal1, 50.0) # now *add* connections up to metal2 connect(metal1, via1) connect(via1, metal2) metal2_errors = antenna_check(gate, metal2, 50.0) ... continue this scheme with further metal layers ...
Plasma induced damage can be rectified by including diodes which create a safe current path for discharging the metal islands. Such diodes can be identified with a recognition layer (usually the diffusion area of a certain kind). You can include such diode recognition layers in the antenna check. If a connection is detected to a diode, the respective network is skipped:
... diode = ... # diode recognition layer connect(diode, contact) errors = antenna_check(gate, metal1, 50.0, diode)
You can also make diode connections decreases the sensitivity of the antenna check depending on the size of the diode. The following specification makes diode connections increase the ratio threshold by 10 per square micrometer of diode area:
... diode = ... # diode recognition layer connect(diode, contact) # each square micrometer of diode area connected to a network # will add 10 to the ratio: errors = antenna_check(gate, metal1, 50.0, [ diode, 10.0 ])
Multiple diode specifications are allowed. Just add them to the antenna_check call.
You can include the perimeter into the area computation for the gate or metal layer or both. The physical picture is this: the side walls of the material contribute to the surface too. As the side wall area can be estimated by taking the perimeter times some material thickness, the effective area is:
A(eff) = A + P * t
Here A is the area of the polygons and P is their perimeter. t is the "thickness" in micrometer units. To specify such a condition, use the following notation:
errors = antenna_check(area_and_perimeter(gate, 0.5), ...)
"area_and_perimeter" takes the polygon layer and the thickness (0.5 micrometers in this case). This notation can be applied to both gate and metal layers. A detailed notation for the usual, area-only case is available as well for completeness:
errors = antenna_check(area_only(gate), ...) # this is equivalent to a zero thickness: errors = antenna_check(area_and_perimeter(gate, 0.0), ...) # or the standard case: errors = antenna_check(gate, ...)
Finally there is also "perimeter_only". When using this specification with a thickness value, the area is computed from the perimeter alone:
A(eff) = P * t
errors = antenna_check(perimeter_only(gate, 0.5), ...)
The error shapes produced by the antenna check are copies of the metal shapes on the metal layers of each network violating the antenna rule.
You can specify a text layer (use "labels" to create one). It will receive error labels describing the measured values and computation parameters for debugging the layout. This option has been introduced in version 0.27.11.
Usage:
See connect for more details.
Usage:
a and b must be polygon or text layers. After calling this function, the Netter regards all overlapping or touching shapes on these layers to form an electrical connection between the materials formed by these layers. This also implies intra-layer connections: shapes on these layers touching or overlapping other shapes on these layers will form bigger, electrically connected areas.
Texts will be used to assign net names to the nets. The preferred method is to use labels to create a text layer from a design layer. When using input, text labels are carried implicitly with the polygons but at the cost of small dummy shapes (2x2 DBU marker polygons) and limited functionality.
Multiple connect calls must be made to form larger connectivity stacks across multiple layers. Such stacks may include forks and joins.
Connections are accumulated. The connections defined so far can be cleared with clear_connections.
Usage:
Use this method to explicitly connect nets even if there is no physical connection. The concept is similar to implicit connection (see connect_implicit). The method gets a list of nets which are connected virtually, even if there is no physical connection. The first version applies this scheme to all cells, the second version to cells matching the cell name pattern. The cell name pattern follows the usual glob style form (e.g. "A*" applies the connection in all cells whose name starts with "A").
This method is useful to establish a logical connection which is made later up on the next level of hierarchy. For example, a standard cell my not contain substrate or well taps as these may be made by tap or spare cells. Logically however, the cell only has one power or ground pin for the devices and substrate or well. In order to match both representations - for example for the purpose of LVS - the dual power or ground pins have to be connected. Assuming that there is a global net "BULK" for the substrate and a net "VSS" for the sources of the NMOS devices, the following statement will create this connection for all cell names beginning with "INV":
connect_global(bulk, "BULK")
...
connect_explicit("INV*", [ "BULK", "VSS" ])
The resulting net and pin will carry a name made from the combination of the connected nets. In this case it will be "BULK,VSS".
The virtual connection in general bears the risk of missing a physical connection. The "connect_explicit" feature therefore checks whether the connection is made physically on the next hierarchy level ("must connect" nets), except for top-level cells for which it is assumed that this connection is made later. A warning is raised instead for top level cells.
Explicit connections also imply implicit connections between different parts of one of the nets. In the example before, "VSS" pieces without a physical connection will also be connected.
The explicit connections are applied on the next net extraction and cleared on "clear_connections".
Usage:
Connects the shapes from the given layer l to a global net with the given name. Global nets are common to all cells. Global nets automatically connect to parent cells throughs implied pins. An example is the substrate (bulk) net which connects to shapes belonging to tie-down diodes. "l" can be a polygon or text layer.
Usage:
This method specifies a net name search pattern, either for all cells or for certain cells, given by a name search pattern. Search pattern follow the usual glob form (e.g. "A*" for all cells or nets with names starting with "A").
Then, for nets matching the net name pattern and for which there is more than one subnet, the subnets are connected. "Subnets" are physically disconnected parts of a net which carry the same name.
This feature is useful for example for power nets which are complete in a cell, but are supposed to be connected upwards in the hierarchy ("must connect" nets). Physically there are multiple nets, logically - and specifically in the schematic for the purpose of LVS - there is only one net. "connect_implicit" now creates a virtual, combined physical net that matches the logical net.
This is general bears the risk of missing a physical connection. The "connect_implicit" feature therefore checks whether the connection is made physically on the next hierarchy level, except for top-level cells for which it is assumed that this connection is made later. A warning is raised instead for top level cells.
The implicit connections are applied on the next net extraction and cleared on "clear_connections". Another feature is connect_explicit which allows connecting differently named subnets in a similar fashion.
Usage:
Specifying a factor of 2 will make all devices being extracted as if the geometries were two times larger. This feature is useful when the drawn layout does not correspond to the physical dimensions.
Usage:
Runs the device extraction for given device extractor class. In the first form, the extractor object is given. In the second form, the extractor's class object and the new extractor's name is given.
The device extractor is either an instance of one of the predefined extractor classes (e.g. obtained from the utility methods such as mos4) or a custom class. It provides the algorithms for deriving the device parameters from the device geometry. It needs several device recognition layers which are passed in the layer hash.
Predefined device extractors are:
Each device class (e.g. n-MOS/p-MOS or high Vt/low Vt) needs its own instance of device extractor. The device extractor beside the algorithm and specific extraction settings defines the name of the device to be built.
The layer hash is a map of device type specific functional names (key) and polygon layers (value). Here is an example:
deep
nwell = input(1, 0)
active = input(2, 0)
poly = input(3, 0)
bulk = make_layer # renders an empty layer used for putting the terminals on
nactive = active - nwell # active area of NMOS
nsd = nactive - poly # source/drain area
gate = nactive & poly # gate area
extract_devices(mos4("NMOS4"), { :SD => nsd, :G => gate, :P => poly, :W => bulk })
The return value of this method will be the device class of the devices generated in the extraction step (see DeviceClass).
Usage:
With this value set to false (the default), "extract_netlist" will raise an exception upon extraction errors. Otherwise, extraction errors will be logged but no error is raised.
Usage:
The LayoutToNetlist object provides access to the internal details of the netter object.
Usage:
Layer names are listed in the LayoutToNetlist (L2N) or LVS database. They are used to identify the layers, the net or device terminal geometries are on. It is usual to have computed layers, so it is necessary to indicate the purpose of the layer for later reuse of the geometries.
It is a good practice to assign names to computed and original layers, for example:
poly = input(...) poly_resistor = input(...) poly_wiring = poly - poly_resistor name(poly_wiring, "poly_wiring")
Names must be assigned before the layers are used for the first time in connect, soft_connect, connect_global, soft_connect_global and extract_devices statements.
If layers are not named, they will be given a name made from the name_prefix and an incremental number when the layer is used for the first time.
name can only be used once on a layer and the layer names must be unique (not taken by another layer).
The layer/datatype or LayerInfo specification is optional and will be used to configure the internal layout. This information is also persisted inside database files. Specifying a layer/datatype information is useful, if a layer is not an original layer, but is to be restored to an actual layout layer later.
Usage:
See for details. The default prefix is "l".
Usage:
If no extraction has been performed yet, this method will start the layout analysis. Hence, all connect, connect_global and connect_implicit calls must have been made before this method is used. Further connect statements will clear the netlist and re-extract it again.
Usage:
a and b must be polygon or text layers. After calling this function, the Netter considers shapes from layer a and b connected in "soft mode". Typically, b is a high-ohmic layer such as diffusion, implant for substate material, also called the "lower" layer.
A soft connection between shapes from layer a and b forms a directional connection like an ideal diode: current can flow down, but now up (not meant in the physical sense, this is a concept).
Hence, two nets are disconnected, if they both connect to the same lower layer, but do not have a connection between them.
The netlist extractor will use this scheme to identify nets that are connected only via such a high-ohmic region. Such a case is typically bad for the functionality of a device and reported as an error. Once, the check has been made and no error is found, soft-connected nets are joined the same way than hard connections are made.
Beside this, soft connections follow the same rules than hard connections (see connect).
Usage:
Connects the shapes from the given layer l to a global net with the given name in "soft mode".
See connect_global for details about the concepts of global nets. See soft_connect for details about the concept of soft connections. In global net soft connections, the global net (typically a substrate) is always the "lower" layer.
Usage:
With this value set to false (the default), it is assumed that the circuit is not used as a top level chip circuit. In that case, for example must-connect nets which are not connected are reported as as warnings. If top level mode is set to true, such disconnected nets are reported as errors as this indicates a missing physical connection.